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1 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 description dual lvpecl or hstl input, 10 differential 1.5v hstl compatible outputs confgurable as dual-channel 10 output or a single- channel 20 output clock driver guaranteed ac parameters over temperature and voltage: ? > 500mhz f max ? < 50ps within device skew ? < 1.5ns propagation delay ? < 700ps t r / t f time low jitter design ? 186fs rms phase jitter 3.3v core supply, 1.8v output supply output enable function available in a 64-pin epad-tqfp features 3.3v 500mhz dual 1:10 hstl fanout buffer/translator with 2:1 mux input precision edge ? sy89827l applications high-performance pcs workstations parallel processor-based systems other high-performance computing communications rev.: f amendment: /0 issue date: july 2010 the sy89827l is a high performance bus clock driver with dual 1:10 or single 1:20 hstl (high speed transceiver logic) output pairs. the part is designed for use in low voltage (3.3v/1.8v) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. the input is multiplexed from either hstl or lvpecl (low voltage positive emitter coupled logic) by the clk_sel pin. the output enables (oe1 & oe2) are synchronous so that the outputs will only be enabled/disabled when they are already in the low state. this avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. the sy89827l features extremely low skew performance of <50ps over temperature and voltage Cperformance previously unachievable in a standard product having such a high number of outputs. the sy89827l is available in a single space saving package, enabling a lower overall cost solution. for applications that require greater hstl fanout capability, consider the sy89824l. typical application circuit sel1 primary/backup clock select (switchover within 2.0ns) l vpecl_clka /l vpecl_clka l vpecl_clkb /l vpecl_clkb primary clock source redundant backup clock source 10 10 10 10 primar y car d redundan t car d system using sy89827l as a switchover circuit from a primary clock to a redundant backup clock in a failsafe application. lvpecl inputs only, shown in this application. precision edge is a registered trademark of micrel, inc. precision edge ?
2 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 functional block diagram 0 1 hstl_clka /hstl_clka l vpecl_clka / l vpecl_clka hstl_clkb /hstl_clkb l vpecl_clkb / l vpecl_clkb clk_sel2 0 1 sel2 sel1 0 1 oe2 oe1 0 1 q 0 C q 9 10 10 /q 0 C /q 9 q 10 C q 19 10 10 /q 10 C /q 19 len d q clk_sel1 len d q q1 vcco /q6 q6 /q5 q5 /q4 q4 /q3 q3 /q2 q2 /q1 /q0 q0 vcco sel2 hstl_clkb /hstl_clkb vcci hstl_clka /hstl_clka clk_sel1 l vpecl_clka / l vpecl_clka gnd oe1 l vpecl_clkb / l vpecl_clkb clk_sel2 oe2 sel1 vcco q7 /q7 q8 /q8 q9 /q9 vcco vcco q10 /q10 q 1 1 /q 1 1 q12 /q12 vcco 64 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 63 6 2 6 1 6 0 5 9 5 8 57 56 5 5 5 4 5 3 5 2 5 1 5 0 49 1 7 18 1 9 2 0 2 1 2 2 2 3 24 25 2 6 2 7 2 8 2 9 3 0 3 1 32 /q18 vcco q13 /q13 q14 /q14 q15 /q15 q16 /q16 q17 /q17 q18 q19 /q19 vcco 64-pin tqfp (h64-1) package/ordering information ordering information (1) package operating package lead part number type range marking finish sy89827lhi h64-1 industrial sy89827lhi sn-pb sy89827lhitr (2) h64-1 industrial sy89827lhi sn-pb sy89827lhy (3) h64-1 industrial sy89827lhy with pb-free pb-free bar-line indicator matte-sn sy89827lhytr (2, 3) h64-1 industrial sy89827lhy with pb-free pb-free bar-line indicator matte-sn notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. 3. pb-free package recommended for new designs.
3 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 oe1 (1) oe2 (1) sel1 (1) sel2 (1) clk_sel1 (1) clk_sel2 (1) q 0 C q9 /q 0 C /q9 q 10 C q19 /q 10 C /q19 1 1 0 0 0 x hstl_clka /hstl_clka hstl_clka /hstl_clka 1 1 0 0 1 x lvpecl_clka /lvpecl_clka lvpecl_clka /lvpecl_clka 1 1 0 1 0 0 hstl_clka /hstl_clka hstl_clkb /hstl_clkb 1 1 0 1 0 1 hstl_clka /hstl_clka lvpecl_clkb /lvpecl_clkb 1 1 0 1 1 0 lvpecl_clka /lvpecl_clka hstl_clkb /hstl_clkb 1 1 0 1 1 1 lvpecl_clka /lvpecl_clka lvpecl_clkb /lvpecl_clkb 1 1 1 0 0 0 hstl_clkb /hstl_clkb hstl_clka /hstl_clka 1 1 1 0 0 1 lvpecl_clkb /lvpecl_clkb hstl_clka /hstl_clka 1 1 1 0 1 0 hstl_clkb /hstl_clkb lvpecl_clka /lvpecl_clka 1 1 1 0 1 1 lvpecl_clkb /lvpecl_clkb lvpecl_clka /lvpecl_clka 1 1 1 1 x 0 hstl_clkb /hstl_clkb hstl_clkb /hstl_clkb 1 1 1 1 x 1 lvpecl_clkb /lvpecl_clkb lvpecl_clkb /lvpecl_clkb 0 1 x 0 0 x low high hstl_clka /hstl_clka 0 1 x 0 1 x low high lvpecl_clka /lvpecl_clka 0 1 x 1 x 0 low high hstl_clkb /hstl_clkb 0 1 x 1 x 1 low high lvpecl_clkb /lvpecl_clkb 1 0 0 x 0 x hstl_clka /hstl_clka low high 1 0 0 x 1 x lvpecl_clka /lvpecl_clka low high 1 0 1 x x 0 hstl_clkb /hstl_clkb low high 1 0 1 x x 1 lvpecl_clkb /lvpecl_clkb low high 0 0 x x x x low high low high truth table note 1. input has internal pull-up floating input = 1.
4 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 pin descriptions internal pin number pin name i/o type p/u pin function 5, 6 hstl_clka input hstl differential clock input selected by clk_sel1, sel1 and sel2. /hstl_clka can be left foating if not selected. floating input, if selected produces an indeterminate output. hstl input signal requires external termination 50?-to-gnd. 2, 3 hstl_clkb input hstl differential clock input selected by clk_sel1, sel1 and sel2. /hstl_clkb can be left foating if not selected. floating input, if selected produces an indeterminate output. hstl input signal requires external termination 50?-to-gnd. 8, 9 lvpecl_clka input lvpecl 75k? differential clock input selected by clk_sel1, sel1 and sel2. /lvpecl_clka pull-down can be left foating. floating input, if selected produces a low at output. requires external termination. see figure 1. 12, 13 lvpecl_clkb input lvpecl 75k? differential clock input selected by clk_sel2, sel1 and sel2. /lvpecl_clkb pull-down requires external termination. see figure 1. 7 clk_sel1 input lvttl/ 11k? selects hstl_clka input when low and lvpecl_clka cmos pull-up input when high. 14 clk_sel2 input lvttl/ 11k? selects hstl_clkb input when low and lvpecl_clkb cmos pull-up input when high. 16 sel1 input lvttl/ 11k? selects input source clka when low and clkb cmos pull-up when high for outputs q0 C q9 and /q0 C /q9. 1 sel2 input lvttl/ 11k? selects input source clka when low and clkb cmos pull-up when high for outputs q10 C q19 and /q10 C /q19. 11 oe1 input lvttl/ 11k? enable input synchronized internally to prevent glitching of the cmos pull-up q0 C q9 and /q0 C /q9 outputs. 15 oe2 input lvttl/ 11k? enable input synchronized internally to prevent glitching of the cmos pull-up q10 C q19 and /q10 C /q19 outputs. 4 vcci power core vcc connected to 3.3v supply. bypass with 0.1f in parallel with 0.01f low esr capacitors as close to vcc pins as possible. 17, 32, 33, vcco power output buffer vcc connected to 1.8v nominal supply. all vcco 40, 41, 48, 49, 64 pins should be connected together on the pcb. bypass with 0.1f in parallel with 0.01f low esr capacitors as close to vcco pins as possible. 10 gnd power ground. 63, 61, 59, 57, 55 q0 C q9 output hstl differential clock outputs from clka when sel1 = low and 53, 51, 47, 45, 43 from clkb when sel1 = high. hstl outputs (q and /q) must be terminated with 50?-to-gnd. q outputs are static when oe1 = low. unused output pairs may be left foating. 62, 60, 58, 56, 54 /q0 C /q9 output hstl differential clock outputs (complement) from clka when sel1 = 52, 50, 46, 44, 42 low and from clkb when sel1 = high. hstl outputs (q and /q) must be terminated with 50?-to-gnd. /q outputs are static high when oe1 = low. unused output pairs may be left foating. 39, 37, 35, 31, 29 q10 C q19 output hstl differential outputs from clka when sel2 = low and from 27, 25, 23, 21, 19 clkb when sel2 = high. hstl outputs (q and /q) must be terminated with 50?-to-gnd. q outputs are static low when oe2 = low. unused output pairs may be left foating. 38, 36, 34, 30, 28 /q10 C /q19 output hstl differential outputs (complement) from clka when sel2 = low 26, 24, 22, 20, 18 and from clkb when sel2 = high. hstl outputs (q and /q) must be terminated with 50?-to-gnd. /q outputs are static high when oe2 = low. unused output pairs may be left foating.
5 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (note 1) power supply voltage (v cci , v cco ) ............... C0.5 to +4.0v input voltage (v in ) ............................................ C0.5 to v cci output current (i out ) ............................................... C50ma lead temperature (t lead , soldering, 20sec.) .......... 260c storage temperature (t s ) ............................ C65 to +150c esd rating, note 3 .................................................... >1kv operating ratings (note 2) supply voltage (v cci ) ..................................................... +3.3v to +3.47v (v cco ) ..................................................... +1.6v to +2.0v ambient temperature (t a ) .......................... C40c to +85c package thermal resistance tqfp ( ja ) exposed pad soldered to gnd, note 4 still-air (multi-layer pcb) ......................................... 23c/w C200lfpm (multi-layer pcb) ..................................... 18c/w C500lfpm (multi-layer pcb) ..................................... 15c/w exposed pad not soldered to gnd (not recommended) still-air (multi-layer pcb) ......................................... 44c/w C200lfpm (multi-layer pcb) ..................................... 36c/w C500lfpm (multi-layer pcb) ..................................... 30c/w tqfp ( jc ) ......................................................... 4.4c/w power supply : t a = C40c to +85c symbol parameter condition min typ max units v cci v cc core 3.13 3.3 3.47 v v cco v cc output 1.6 1.8 2.0 v i cci i cc core no load 140 170 ma hstl input/output: v cci = 3.3v 5%, v cco = 1.8v 10%, t a = C40c to +85c symbol parameter condition min typ max units v oh output high voltage note 5 1.0 1.2 v v ol output low voltage note 5 0.2 0.4 v v ih input high voltage v x +0.1 1.6 v v il input low voltage C0.3 v x C0.1 v v x input crossover voltage 0.68 0.9 v i ih input high current +20 C350 a i il input low current C500 a note 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. note 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. note 3. devices are esd sensitive. handling precautions recommended. note 4. it is highly recommended to solder the exposed pad of the epad-tqfp package to a ground plane on the pcb for maximum thermal effciency. note 5. outputs loaded with 50?-to-ground. dc electrical characteristics
6 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 lvpecl input: v cci = 3.3v 5%, t a = C40c to +85c symbol parameter condition min typ max units v ih input high voltage (single-ended) v cci C1.165 v cci C0.880 v v il input low voltage v cci C1.945 v cci C1.625 v v pp minimum input swing (lvpecl_clk) note 6 300 mv v cmr common mode range (lvpecl_clk) note 7 gndi +1.8 v cci C0.4 v i ih input high current 150 a i il input low current 0.5 a note 6. the v pp (min.) is defned as the minimum input differential voltage which will cause no increase in the propagation delay. note 7. v cmr is defned as the range within which the v ih level may vary, with the device still meeting the propagation delay specifcation. the num- bers in the table are referenced to v cci . the v il level must be such that the peak-to-peak voltage is less than 1.0v and greater than or equal to v pp (min.). v cmr range varies 1:1 with v cci . v cmr (min) is fxed at gndi +1.8v cmos/lvttl inputs : v cci = 3.3v 5%, v cco = 1.8v 10%, t a = C40c to +85c symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current +20 C250 a i il input low current C600 a dc electrical characteristics
7 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 v cci = 3.3v 5%, v cco = 1.8v 10%, t a = C40c to +85c, all outputs loaded, unless noted. symbol parameter condition min typ max units f max maximum toggle frequency note 2 500 mhz t pd differential propagation delay note 3 1.0 1.3 1.5 ns v pp minimum input swing, note 4 hstl 200 mv pecl 150 mv t sw switchover time clk_sel-to-q 1.6 2.0 ns sel-to-q 1.4 1.75 ns t jitter rms phase jitter output: 622mhz integration range: 12khz - 20mhz 186 fs t s(oe) output enable set-up time note 5 1.0 ns t h(oe) output enable hold time note 5 0.5 ns t skew within device skew note 6 0c to +85c 25 50 ps C40c 35 75 ps part-to-part skew note 7 400 ps t r , t f output rise/fall times 450 700 ps (20% to 80%) note 1. outputs loaded with 50?-t- ground. note 2. f max is defned as the maximum toggle frequency, measured with a 750mv lvpecl/hstl input. hstl output swing is > 400mv. note 3. differential propagation delay is defned as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. note 4. the v pp (min.) is defned as the minimum input differential voltage which will cause no increase in the propagation delay. note 5. oe set-up time is defned with respect to the rising edge of the clock. oe high-to-low transition ensures outputs remain disabled during the next clock cycle. oe low-to-high transition enables normal operation of the next input clock. note 6. the within-device skew is defned as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. this parameters includes within bank skew and bank-to-bank skew. note 7. the part-to-part skew is defned as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. ac electrical characteristics (note 1) phase noise 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -1 10 -120 -130 -140 -150 -160 -170 -180 -190 -200 10 100 1k 10k 100k 1m 10m 100m offset frequenc y (hz) noise power (dbc/hz) phase noise plot: 622mhz @ 3.3v rms phase jitter (random) 12khz to 20mhz: 186fs (typical)
8 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics 0 200 400 600 800 1000 1200 1400 1600 1800 2000 -5 0 -2 5 0 2 5 5 0 7 5 100 propagation delay (ps) temperature ( c) nominal propagation delay vs. temperature hstl input lvpecl input 0 200 400 600 800 1000 1200 1400 1600 1800 -5 0 -2 5 0 2 5 5 0 7 5 100 switchover time (ns) temperature ( c) clk_sel switchover time vs. temperature v cci = 3.3v, v cco = 1.8v, t a = 25c, unless otherwise stated. 0 100 200 300 400 500 600 700 800 0 20 0 40 0 60 0 80 0 1000 output amplitude (mv) frequency (mhz) output amplitude vs. frequency 0 200 400 600 800 1000 1200 1400 0 20 0 40 0 60 0 80 0 1000 propagation delay (ns) input amplitude (mv) propagation delay vs. input amplitude pecl input hstl input
9 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 functional characteristics v cci = 3.3v, v cco = 1.8v, t a = 25c, unless otherwise stated.
10 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 hstl outputs lvpecl/hstl inputs figure 1. simplifed lvpecl input stage figure 2. simplifed hstl input stage q out /q out 800mv figure 3. output driver signal levels (single-ended) q out /q out 1.6v q ou t /q out t figure 4. output driver signal levels (differential) part number function data sheet link sy89809l 3.3v 1:9 high-performance, low-voltage bus clock driver www.micrel.com/product-info/products/sy89809l.shtml sy89824l 3.3v 1:22 high-performance, low-voltage bus clock driver www.micrel.com/product-info/products/sy89824l.html exposed pad application note www.amkor.com/products/notes_papers/epad.pdf m-0317 hbw solutions www.micrel.com/product-info/products/solutions.shtml mic3775 750ma cap low-voltage low-dropout regulator www.micrel.com/product-info/products/mic3775.shtml related product and support documentation
11 precision edge ? sy89827l micrel, inc. m9999-073010 hbwhelp@micrel.com or (408) 955-1690 64-pin epad-tqfp (die up) (h64-1) +0.05 C 0.05 +0.002 C 0.002 +0.006 C 0.006 +0.012 C 0.012 +0.002 C 0.002 +0.15 C 0.15 +0.03 C 0.03 +0.05 C 0.05 +0.012 C 0.012 +0.05 C 0.05 p a c kage ep- exposed p ad die compside island heat dissipation he a vy copper plane he a vy copper plane v ee v ee heat dissipation pcb thermal consideration for 64-pin epad-tqfp package (always solder, or equivalent, the exposed pad to the pcb) micrel, inc. 2180 fortune drive san jose, ca 95131 usa t e l + 1 (408) 944-0800 f a x + 1 (408) 944-0970 w e b http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifcations at any time without notifcation to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signifcant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is at purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2002 micrel, incorporated.

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